Publication Details

Abstract

Modern applications such as image processing, machine learning, and multimedia can tolerate small computational errors, making approximate computing an effective way to improve hardware efficiency. This work presents a family of 8-bit approximate multipliers with 15 configurable accuracy levels based on Partial Bit OR (PBO) approximation techniques. The proposed designs use recursive, bit-wise, and hybrid methods to simplify partial product generation and accumulation, reducing hardware complexity, power consumption, and computation time. To further improve speed, a Carry Increment Adder (CIA) is used in the final addition stage, enabling faster carry propagation and lower delay than conventional adders. The proposed multipliers are evaluated in terms of area, delay, power, power-delay product (PDP), and error performance. Results show that the CIA significantly reduces multiplication latency and improves energy efficiency while maintaining acceptable accuracy. Compared with existing approximate multipliers, the proposed designs provide a better balance between accuracy, speed, and hardware cost, making them suitable for energy-efficient applications such as digital signal processing, machine learning, and embedded systems.