Publication Details
Keywords: Semiconductor manufacturing, yield diagnosis, yield prediction, yield tuning, Bayesian optimization
Abstract
Yield improvement in emerging semiconductor devices is a critical yet challenging phase in transitioning from laboratory prototypes to large-scale fabrication. Conventional yield tuning methods are often time-consuming, resource-intensive, and limited by the scarcity of experimental data during the early research stage. To overcome these challenges, a synthetic semiconductor yield dataset was generated and subjected to preprocessing steps including null value removal, duplicate elimination, normalization, and feature selection using SelectKBest. A series of base models—XGBoost, Random Forest, LightGBM, SVR, KNN, Gaussian Process, Naive Bayes, Ridge, Lasso, ElasticNet, and MLP—were developed, followed by optimized models such as XGBoost (GridSearchCV), Random Forest (GridSearchCV), and LightGBM variants (GOSS, DART). Additionally, to further enhance predictive accuracy, ensemble methods including a Voting Regressor (RF + GB + XGBoost) and a Stacking Regressor were implemented. Model performance was evaluated using Explained Variance, Mean Absolute Error (MAE), Root Mean Square Error (RMSE), and R² metrics. The Voting Regressor achieved the highest performance with an Explained Variance and R² of 71.7%, MAE of 0.080, and RMSE of 0.096. Cross-validation combined with GridSearch and Bayesian optimization was applied to XGBoost and Random Forest for parameter tuning. Furthermore, a Flask-based interface was developed to enable user interaction with the trained models, allowing real-time yield prediction and visualization supported by Explainable AI tools such as LIME and SHAP.
References
- [1] Sankaran, K., Mosleh, A., & Hakim, K. (2025, January). Semiconductor Parametric Yield Prediction: A Combination of Machine Learning and Physics-Informed Approach. In 2025 Annual Reliability and Maintainability Symposium (RAMS) (pp. 1-6). IEEE. [2] Islam, M. N., Islam, M. T., & Dhali, M. A. (2025, April). Classification and Prediction of Wafer Yield Using Gradient Boosting Algorithms: A Focus on Lithography Inline Parameters. In 2025 IEEE 4th International Conference on Computing and Machine Intelligence (ICMI) (pp. 1-6). IEEE. [3] Song, Y., Lee, S., & Lee, D. H. (2025, August). Stacking Ensemble method for Wafer Yield Prediction in Semiconductor Manufacturing. In 2025 IEEE 21st International Conference on Automation Science and Engineering (CASE) (pp. 1184-1188). IEEE. [4] Song, M. L. Y., Sharma, A., & Chin, C. S. (2025). Wafer Region Yield Prediction: Employing Majority Under-Sampling and Output Binarization on Low-Yield Threshold. IEEE Access. [5] Parmar, T. Process Optimization in Semiconductor Manufacturing: The Role of Big Data Analytics in Yield Improvement. [6] H.-W. Xu, Q.-H. Zhang, Y.-N. Sun, Q.-L. Chen, W. Qin, Y.-L. Lv, and J. Zhang, “A fast ramp-up framework for wafer yield improvement in semiconductor manufacturing systems,” J. Manuf. Syst., vol. 76, pp. 222–233, Oct. 2024, doi: 10.1016/j.jmsy.2024.07.001. [7] Y. P. Tsai, Y. H. Chang, J. Wang, D. Trivkovic, K. Ronse, and R. H. Kim, “A yield prediction model and cost of ownership for productivity enhancement beyond imec 5 nm technology node,” DTCO Comput. Patterning, 2022. [8] H.-W. Xu, W. Qin, Y.-L. Lv, and J. Zhang, “Data-driven adaptive virtual metrology for yield prediction in multibatch wafers,” IEEE Trans. Ind. Informat., vol. 18, no. 12, pp. 9008–9016, Dec. 2022, doi: 10.1109/TII.2022.3162268. [9] S. Mao et al., “A yield-improvement method for millimeter-wave GaN MMIC power amplifier design based on load—Pull analysis,” IEEE Trans. Microw. Theory Techn., vol. 69, no. 8, pp. 3883–3895, Aug. 2021. [10] P. Stich, M. Wahl, P. Czerner, C. Weber, and M. Fathi, “Yield prediction in semiconductor manufacturing using an AI-based cascading classification system,” in Proc. IEEE Int. Conf. Electro Inf. Technol. (EIT), Jul. 2020, pp. 609–614. [11] Y. Ding et al., “A device design for 5 nm logic FinFET technology,” China Semicond. Technol. Int. Conf. (CSTIC), 2020. [12] B. Shahriari, K. Swersky, Z. Wang, R. P. Adams, and N. de Freitas, “Taking the human out of the loop: A review of Bayesian optimization,” Proc. IEEE, vol. 104, no. 1, pp. 148–175, Jan. 2016. [13] J. Snoek, H. Larochelle, and R. P. Adams, “Practical Bayesian optimization of machine learning algorithms,” in Proc. Adv. Neural Inf. Process. Syst., vol. 25, 2012. [14] M. Melhem, B. Ananou, M. Ouladsine, and J. Pinaton, “Regularized regression models to predict the product quality in multistep manufacturing,” in Proc. 5th Int. Conf. Syst. Control (ICSC), May 2016, pp. 31–36. [15] B. Lenz and B. Barak, “Data mining and support vector regression machine learning in semiconductor manufacturing to improve virtual metrology,” 46th Hawaii Int. Conf. Syst. Sci., 2013. [16] T. Chen, “An ANN approach for modeling the multisource yield learning process with semiconductor manufacturing as an example,” Comput. Ind. Eng., vol. 103, pp. 98–104, Jan. 2017. [17] C.-F. Chien, C.-Y. Hsu, and P.-N. Chen, “Semiconductor fault detection and classification for yield enhancement and manufacturing intelligence,” Flexible Services Manuf. J., vol. 25, no. 3, pp. 367–388, Sep. 2013. [18] J. Moyne, J. Samantaray, and M. Armacost, “Big data capabilities applied to semiconductor manufacturing advanced process control,” IEEE Trans. Semicond. Manuf., vol. 29, no. 4, pp. 283–291, Nov. 2016. [19] G. Wang, R. M. Hasani, Y. Zhu, and R. Grosu, “A novel Bayesian network-based fault prognostic method for semiconductor manufacturing process,” in Proc. IEEE Int. Conf. Ind. Technol. (ICIT), Mar. 2017, pp. 1450–1454. [20] K. B. Lee, S. Cheon, and C. O. Kim, “A convolutional neural network for fault classification and diagnosis in semiconductor manufacturing processes,” IEEE Trans. Semicond. Manuf., vol. 30, no. 2, pp. 135–142, May 2017.